A new approach to ward off Error Propagation Effect of AES – Redundancy Based Technique Redefined

Advanced Encryption Standard (AES) [1, 2] is a great research challenge. It has been developed to replace the Data Encryption Standard (DES). AES suffers from a major limitation of Error propagation effect. To tackle this limitation, two methods are available. One is Redundancy Based Technique and the other one is Bite Based Parity Technique. The first one has a significant advantage of correcting any error on definite term over the second one but at the cost of higher level of overhead and hence lowering the processing speed. In this paper we have proposed a new approach based on the Redundancy Based Technique that would certainly speed up the process of reliable encryption and hence the secured communication. Keywords Advanced Encryption Standard, Error Propagation Effect, Redundancy Based Technique, Longitudinal Redundancy Check Cod

Low-Power High-Speed Double Gate 1-bit Full Adder Cell

In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit able to operate at very low voltage and maintain the proper output voltage swing and also balanced the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology). In the proposed technique the most time-consuming and power consuming XOR gates and multiplexor are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94µW at 1.8V supply voltage and frequency of 500 MHz, which is less than other conventional methods. Power, delay, and area are optimized by using pass transistor logic and verified using SPICE simulation tool at desired broad frequency range. It is also observed that the proposed designs successfully utilized in many cases, especially whenever the lowest power consumption and delay are aimed

Two-way Mechanism to Enhance Confidentiality and Accuracy of Shared Information

As such internet and information technology have influenced the human life significantly thus the current technology cannot solely assure the security of shared information. Hence, to fulfil such requirements mass amount of research have been undertaken by various researchers among which one of the mechanisms is the use of dynamic key rather than static one. In this regard, we have proposed a method of key generation to provide the dynamic keys. The scheme not only can change the key but also provide the error control mechanism. At the end of this paper, a comparison with the existing techniques has also been made to prove the efficiency of the proposed scheme

Pre-emptive Dynamic Source Routing: A Repaired Backup Approach and Stability Based DSR with Multiple Routes

DSR algorithm finds out the best path for communicating between two nodes in a highly dynamic environment. Since, the environment changes frequently, the probability of established path breakage is also high. Again, as the breakage possibility increases, a new route has to be discovered every time .In order to avoid path discovery every time, we propose the modification of the existing DSR algorithm. In this paper we propose an enhancement of the DSR protocol based on a backup route(second best route) which will be provided by the destination node to the source node along with the best route during the process of path discovery. During the path maintenance process, in case any intermediate node identifies that the signal strength falls below a threshold i.e. the established route is about to break, the intermediate node sends a caution message to the source node. The source node switches the communication through the backup path , apprehending that the established route is about to break. As the communication through the backup route takes place, the previous route is repaired, if possible and acts as the new backup route. This process of toggling between backup route and established route reduces the call for path discovery to some extent. The stability in consideration of failure of common link and nodes in the back up repaired algorithm has been investigated with new algorithm for stable route selection

Sir Jagadish Chandra Bose: Tribute on his 160^th Birth Anniversary

30-31Physicist, Botanist, Biologist, Archaeologist, and Radio & Microwave Technologist – Jagadish Chandra Bose was all this and much more

Minterms Generations Algorithm Using Weighted Sum Method

<p>The paper presents an exact algorithms for minterms generation. These algorithms are exact in the sense that they guarantee the minimum number of minterms terms in the final solution. Using this algorithm minterms may be generating from any minimized sum of product terms of multiple input variables. A flow chart is prepared to generate minterms called Minterms Generator. The Minterms Generator able to generate minterms from any number minimized sum of product terms of any number of input variables. This algorithm easily implement in computer programming. The completeness, consistency, and finite convergence of the algorithm are proven. Representative results from the computer program implementation of the algorithm are presented in this paper.</p

Design and characterization of a tunable patch antenna loaded with capacitive MEMS switch using CSRRs structure on the patch

In this paper, the design and characterization of a tunable patch antenna loaded with complementary split ring resonators (CSRRs) on the patch have been realized. To achieve tunable resonant frequency, bandwidth and radiation pattern, the antenna is further loaded with coplanar waveguide (CPW) on which Microelectromechanical System (MEMS) capacitive switches are placed periodically. The tunable property is achieved, when the switches moves from up state with the capacitive gap 1.5 μm to down state having capacitive gap of 1 μm. A parametric analysis has been presented to check the sensitivity of the antenna in terms of S11 parameter by varying different parameters of the MEMS switches and CSRRs. This work, strives to improve the degree of reconfigurability with increase in the number of switches. The value of actuation voltage to move switch from up to down state is 10.4 V, which is very low over the other design. The switches exhibit fundamental frequency 14.6 kHz, switching time 28.59 μs, and capacitance ratio 15.27. Simulation has been carried out in Ansoft HFSS v. 13 and the distinct characterization property of the tunable antenna is shown through simulation

Minterms Generations Algorithm Using Weighted Sum Method

<p>Digital Electronics Minimization Minterm Generation</p

Constraints Analysis for Minimization of Multiple Inputs Logic Programming

<p>Minimization of logic functions by computer programs are considered traditionally to be difficult and tedious as the incorporation of full logic negation tends to super-exponential time complexity. The paper presents constrains for minimization of logic circuits. Using these analysis minimized sum of products terms may be generating from any given sum of product terms of multiple input variables. For a new algorithm for minimization using computer programming must be overcome these problem presented. We also discuss the scope heuristic minimization technique over the exact minimization technique.</p

Simplification of Switching Functions Using Hex-Minterms

We propose a systematic approach for simplification of two-level multiple inputs logic circuits. In this study, new procedures and algorithms are presented for the derivation and simplification of digital switching circuits. In contrast to the other methods, the proposed technique is quite simple technique. Representation and simplification of switching circuit are proposed here by using hexadecimal code instead of decimal coded minterms. The new procedure is based on tabular techniques for software implementation and Karnaugh map for manual simplification. By virtue of representation in hexadecimal code, literals are forming a pair of maximum four variables. Each digit of hexadecimal minterms are used to detect logic adjacency by direct comparing with other minterms. A logic adjacency chart for hex-minterms is proposed herein for manual simplification and an algorithm is proposed for computer implementation. The proposed method is the fast and exact procedure of minimization. The new approach prevents manipulations error and effectively reduced checking of 1 in each group. The cost of the minimal expression is same with the other methods, but the proposed method effectively reduces the complexity of simplification. The proposed methods are efficient in terms of simplicity and less laborious. The proposed technique is suitable for manual computation as well as computer implementation